Lateral patterning

ABSTRACT

A method and structure for forming an integrated circuit chip having at least one opening in a substrate includes forming an opening having vertical walls in the substrate, protecting a first portion of the vertical walls of the opening, leaving a second portion of the vertical walls unprotected, and laterally patterning the second portion of the opening to change a shape or property of the opening.

FIELD OF THE INVENTION

[0001] The present invention generally relates to the formation ofself-aligned structures in integrated circuit devices and moreparticularly to generating a lateral mask followed by lateral etching,deposition, diffusion or epitaxy.

DESCRIPTION OF RELATED ART

[0002] Spacers are broadly used in the conventional formation ofintegrated circuit devices. The spacers are self-aligned structuresgenerated laterally adjacent to an existing structure. The spacers canbe used as a mask for vertical processing (e.g., as etch masks orimplant masks).

[0003] However, conventional processing is limited to the formation ofvertical features/structures self-aligned with the spacers. This limitsthe designers ability to form structures laterally. The inventionovercomes this problem as discussed below.

SUMMARY OF THE INVENTION

[0004] It is, therefore, an object of the present invention to provide astructure and method for forming an integrated circuit chip having atleast one opening in a substrate which includes forming an openinghaving vertical walls in the substrate, protecting a first portion ofthe vertical walls of the opening, leaving a second portion of thevertical walls unprotected, and laterally processing the second portionof the opening to change the shape of the opening. The laterallyprocessing can include an isotropic wet etch, an isotropic dry etch oran anisotropic wet etch, selective deposition processes, selectiveepitaxial processes, or diffusion. The protecting includes forming amask over the first portion of the vertical walls. The first portion canbe the upper or lower portion of the opening. The first portion and thesecond portion can be alternating portions along a depth of the opening.

[0005] A second embodiment of the invention is a structure and method offorming an integrated circuit chip having at least one opening in asubstrate which includes forming an opening having vertical walls in thesubstrate, protecting a first portion of the vertical walls of theopening, leaving a second portion of the vertical walls unprotected, andlaterally patterning the second portion of the opening to form a step inthe opening.

[0006] A third embodiment of the invention is a method of forming anintegrated circuit chip having at least one transistor which includesforming an opening having vertical walls in a semiconductor substrate,protecting a first portion of the vertical walls of the opening, leavinga second portion of the vertical walls unprotected, laterally patterningthe second portion of the opening to form a step in the opening, anddoping selected portions of the step to form two conductive regionsseparated by a semiconductive region. In the presence of an adjacentvoltage field, the semiconductive region changes its conductivity andperforms a switching operation in combination with the conductiveregions.

[0007] Yet another embodiment of the invention is a method of forming anintegrated circuit chip having at least one opening in a substrate whichincludes forming an opening having vertical walls in the substrate,protecting first portions of the vertical walls of the opening, leavingsecond portions of the vertical walls unprotected, wherein the firstportions alternate with the second portions, and laterally etching thesecond portions of the opening to change a shape or property of theopening.

[0008] A further embodiment is an integrated circuit having at least onetrench capacitor where the trench capacitor includes an opening havingvertical sides, the vertical sides including a plurality of lateralopenings, an insulator lining the opening and a conductor filling theopening. The lateral openings can be rectangular, v-shaped or curvedopenings in cross-section. The lateral openings increase a surface areaand capacitance of the trench capacitor.

[0009] The invention is superior to conventional formation techniquesbecause it allows for self-aligned patterning in the third dimension(i.e., laterally). Also, the size of the structures can be easilyadjusted by altering of the depth of the sacrifical and/or maskmaterial, as discussed above. The depositions of the masking andsacrificial materials can be controlled much more precisely with theinvention than with conventional lithographic techniques. This isespecially true when the dimensions of the structures decrease.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The foregoing and other objects, aspects and advantages will bebetter understood from the following detailed description of preferredembodiments of the invention with reference to the drawings, in which:

[0011]FIG. 1 is a schematic diagram of a partially formed structureaccording to the invention;

[0012]FIG. 2 is a schematic diagram of a partially formed structureaccording to the invention;

[0013]FIG. 3 is a schematic diagram of a partially formed structureaccording to the invention;

[0014]FIG. 4A is a schematic diagram of a structure according to theinvention;

[0015]FIG. 4B is a schematic diagram of a partially vertical transistor;

[0016]FIG. 5 is a schematic diagram of a partially formed structureaccording to the invention;

[0017]FIG. 6 is a schematic diagram of a partially formed structureaccording to the invention;

[0018]FIG. 7 is a schematic diagram of a partially formed structureaccording to the invention;

[0019]FIG. 8 is a schematic diagram of a partially formed structureaccording to the invention;

[0020]FIG. 9 is a schematic diagram of a partially formed structureaccording to the invention;

[0021]FIG. 10 is a schematic diagram of a structure according to theinvention;

[0022]FIG. 11 is a schematic diagram of a partially formed structureaccording to the invention;

[0023]FIG. 12A is a schematic diagram of a partially formed structureaccording to the invention;

[0024]FIG. 12B is a schematic diagram of a partially formed structureaccording to the invention;

[0025]FIG. 12C is a schematic diagram of a partially formed structureaccording to the invention;

[0026]FIG. 13A is a schematic diagram of a deep trench capacitorstructure according to the invention;

[0027]FIG. 13B is a schematic diagram of a deep trench capacitorstructure according to the invention;

[0028]FIG. 13C is a schematic diagram of a deep trench capacitorstructure according to the invention;

[0029]FIG. 14 is a schematic diagram of the beginning of generation ofvertical transistors according to the invention;

[0030]FIG. 15 is a schematic diagram of the next step in generation ofvertical transistors according to the invention;

[0031]FIG. 16 is a schematic diagram of another step of generation ofvertical transistors according to the invention;

[0032]FIG. 17 is a schematic diagram of the next stage of generation ofvertical transistors according to the invention;

[0033]FIG. 18 is a schematic diagram of yet another stage of generationof vertical transistors according to the invention;

[0034]FIG. 19 is a schematic diagram of the next phase of generation ofvertical transistors according to the invention;

[0035]FIG. 19 is a schematic diagram of another phase of generation ofvertical transistors according to the invention;

[0036]FIG. 20 is a schematic diagram of the finished devices aftergeneration of vertical transistors according to the invention;

[0037]FIG. 21 is another schematic diagram of the finished devices;

[0038]FIG. 22 is a schematic diagram of the first stage in the formationof a silicon bridge for a bridge device according to the invention;

[0039]FIG. 23 is a schematic diagram of the second stage in theformation of a silicon bridge;

[0040]FIG. 24 is a schematic diagram of the formation of a siliconbridge during lateral patterning according to the invention;

[0041]FIG. 25 is a schematic diagram of the formation of a siliconbridge after lateral patterning according to the invention;

[0042]FIG. 26 is a schematic diagram of the free-standing silicon bridgedevice; and

[0043]FIG. 27 is a flow diagram illustrating a preferred method of theinvention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

[0044] Referring now to the drawings, and more particularly to FIGS.1-4, an embodiment of the invention is illustrated. FIG. 1 illustrates asubstrate 10 which can be a conductor, insulator or semiconductor. In apreferred example, the substrate 10 is a mono-crystalline siliconinsulator. An opening 11 is formed in the substrate 10 using any of awide variety of conventional methods, such as masking and etchingprocesses.

[0045]FIG. 2 illustrates a masking material 20 formed on the horizontalsurfaces of the substrate 10. The masking material can comprise anyconventional masking substance (such as an oxide, nitride, etc.). Themasking material 20 can be deposited to be formed only on the horizontalsurfaces of the substrate 10 using for example, a mixture of silane,oxygen and argon gases in a high density plasma reactor.

[0046] In FIG. 3, the inventive lateral patterning process is performed.This process involves an isotropic wet or dry etch or an anisotropic wetetch. The chemical composition of the etching solution used can compriseany conventional etching agent, such as H₃PO₄ for an isotropic etch ofSi₃N₄, F (from NF₃) for an isotropic etch of Si in a chemical dry etch,and is preferably NH₄OH for an anisotropic etch of Si. This processselectively removes material from the vertical surfaces (e.g., 110) ofthe substrate 10 as shown by the arrows 30 in FIG. 3. Selectivities ofseveral hundreds to one are possible.

[0047] The masking material 20 is then removed using a selectivesolution which dissolves the mask material 20 but does not affect thesubstrate material 10. The selective solution can comprise anyconventional dissolving solution, such as a HF containing solution andpreferably comprises 40:1 diluted HF.

[0048] The remaining structure, shown in FIG. 4A, includes a step 40which can be advantageously used in subsequent processing to formstructures such as a partially vertical transistor, as shown in FIG. 4B.More specifically, FIG. 4B illustrates regions 44, 45 of the step 40which have been doped to have a conductive state. The partially verticaltransistor could be formed in a semiconductive substrate. Therefore, theregion 46 would comprise semiconductor material. In operation, oneelectrical contact 41 would be connected to another electrical contact42 by the application of voltage to a gate conductor region 43 adjacentthe semiconductor 46. The voltage in the gate conductor region 43 wouldchange the conductivity of the semiconductor region 46 from conductiveto non-conductive or, alternatively, from non-conductive to conductive,to perform a switching operation.

[0049] FIGS. 5-8 illustrate a second embodiment of the invention. Morespecifically, beginning with the structure shown in FIG. 2, spacers 50are formed as shown in FIG. 5. The spacers can comprise any conventionalmaterial and are preferably formed of a material which can beselectively removed with respect to the substrate 10 and the mask 20.For example, the spacers can comprise SiN or polysilicon and arepreferably formed of SiN. The spacers are generally formed by depositingthe spacer material and subsequently removing the spacer material fromhorizontal surfaces using an anisotropic reactive ion etching (RIE)process which allows the material to remain only on vertical surfaces,thereby creating the spacers 50.

[0050] A portion of the mask 20 within the opening 11 is removed asshown by item 60 in FIG. 6. This process also removes the mask 20 fromother horizontal surfaces, except those areas protected by the spacers50. For example, a reactive ion etch (RIE) which is selective to themask material 20 (e.g., CHF₃, CF₄, C₄F₈, O₂, etc.) can be used to removethe mask material 20, without affecting the substrate 10, as shown inFIG. 6. The spacers 50 can then be removed and the substrate 10 can beetched further as shown by item 70 in FIG. 7 to extend the opening 60below the level of the lowermost mask 20. Once again, a selective ionetching process (e.g., NF₂, HBr, or O₂) can be used to form the opening70 without damaging the masks 20.

[0051] As shown in FIG. 8, the inventive lateral patterning process(discussed above) is used to form the openings 80, 81. The masks 20 canthen be removed. The remaining structure is especially useful in lowresistance buried bit-line formations and other similar applications.

[0052] An alternative to the previous embodiment is shown in FIGS. 9-10.More specifically, in FIG. 9, a sacrificial material 91 (e.g.,boro-silicate glass (BSG)) 91 and a mask 92 (e.g.,tetraethylorthosilicate (TEOS)) are deposited in an opening 90 in thesilicon 10. Then an opening 93 is formed in the mask 92, usingconventional methods, such as those discussed above. The mask 92 staysin place during selective removal of the sacrificial material 91 fromthe bottom of the trench and the inventive lateral patterning processforms the opening 100 to complete a bottle shape for a bottle shapedcapacitor storage trench shown in FIG. 10. After the opening 100 isformed, a node dielectric is formed by conventional means and the innearelectrode is formed by conventional means. The structure is very usefulfor the subsequent formation of self-aligned bottle trench capacitorcells for DRAMs and other similar devices.

[0053] An important feature is that the upper portion 94 of the bottleopening 100 and the lower portion 95 of the bottle opening 100 areself-aligned by the inventive process. Further, the depth of the largerportion of the “bottle” is determined by the depth of the sacrificialmaterial 91 within the opening 90, which is easily controlled byconventional deposition processing.

[0054] Another embodiment of the invention is shown in FIGS. 11-13C. InFIG. 11, the opening 11 within the substrate is filled with alternatinglayers of the mask material 20 and a sacrificial material 110 such asthe boron silicate glass (BSG) mentioned above. More specifically, asmall amount of the mask material 20 is deposited in the bottom of theopening 11, then a small amount of the sacrificial material 110 isdeposited, then more of the mask material 20 followed by more of thesacrificial material 110 is deposited and the process is continued untilthe opening 11 is filled with alternating layers of mask material 20 andsacrificial material 110.

[0055] Then, an opening 111 is formed through the alternating layers andinto the substrate 10 below the bottom most layer of mask material 20(as indicated by item 112). The opening 111 is smaller than the opening11 to allow the alternating layers to remain on the side walls of theopening 11. The sacrificial material 110 is then removed and theinventive lateral patterning process is used to create the lateralopenings 120, as shown in FIG. 12A.

[0056] In FIG. 12A an isotopic etch is utilized to form the lateralopenings 120 which are rectangular in cross-section. The openings 120are rectangular in cross-section because the structure is aligned withthe <111> plane. To the contrary, the same isotopic etching produces theV-shaped openings 121 shown in FIG. 12B when the structure is aligned inthe <100> plane. FIG. 12C illustrates another embodiment utilizinganisotopic etching which produces rounded lateral openings 122.

[0057] The structures shown in the FIGS. 12A, 12B, and 12C are extremelyuseful in forming deep trench devices that have increased capacitance.More specifically, as shown in FIGS. 13A, 13B, and 13C, the opening 111,120-122 is lined with a thin insulator (e.g., an oxide or nitride) layer130 as the dielectric of the capacitor and the remainder of the opening111 is filled with a conductor 130 (e.g., metal, alloy, polysilicon,etc.) using well known conventional processes to form the innerelectrode.

[0058] The structures formed according to the invention are superior toconventional structures. For example, the deep trench capacitor shown inFIGS. 13A, 13B, and 13C have a substantially increased surface areabetween the insulator 130 and the conductor 131 which produces adramatic increase in the capacitance of the capacitor. Further, theremaining structures which can be formed using the inventive lateralpatterning systems disclosed herein are advantageous over conventionalstructures because the self alignment is to the bottom of the initialtench. That results in a more uniform capacitance distribution.

[0059] FIGS. 14-21 illustrate one example of using the invention to formpairs of vertical transistors. More specifically, FIG. 14 illustrates anopening 140 in a substrate 10. In FIG. 15, the opening 140 is filledwith alternating layers of mask material 150, 152 and sacrificialmaterial 151 formed as discussed above. In FIG. 16, an opening 160 isformed through the layers 150-512 and in FIG. 17, the inventive lateralpatterning process (e.g., the removal of the sacrificial material 151)produces an opening 171. The height of opening 171 is determined by thedepth 153 of the layer of sacrificial material 151, as shown in FIG. 15,which, again, is easily controlled by conventional deposition processes.

[0060] In addition, in FIG. 17, a gate insulator 171 (e.g., oxide) canbe formed along the sides of the opening. Then, in FIG. 18, the opening160 is filled with a conductor 180, such as polysilicon, metal, alloy,etc. In FIG. 19, an opening 190 is formed to remove the conductor 180from the center of the structure. This produces alternating layers ofmask material 151, 152 and conductor 180. The mask material 151, 152 isthen removed, as shown in FIG. 20, and the source and drain regions 201are doped, using conventional methods. For example, the source/drainregions could be doped n+ or p+, 1E₂O/cm³ or higher, by diffusion orother well known methods.

[0061] An important feature of this embodiment is that the height 200 ofthe conductor 180 is determined by the deposition parameters of thesacrificial material 151. More specifically, the height 153, shown inFIG. 15 will control of the height 200 shown in FIG. 20. Therefore, thesize of the conductor 180 is very easily controlled with the inventionby simply altering the deposition parameters of the sacrificial material151, as shown in FIG. 15.

[0062] In FIG. 21, the shallow trench isolation regions (STI) 210 areformed, as is well known in the art, to complete the transistorstructure. Therefore, as shown in FIG. 21, the above process producespairs of vertical transistors which have dimensions that are tightlycontrolled by the easily adjusted deposition process of the alternatingmask and sacrificial material layers 150-152 shown in FIG. 15.

[0063] FIGS. 22-26 illustrate yet another example of how the inventioncan be used to improve the formation of electronic devices. Morespecifically, this embodiment forms a silicon trench which can be used,for example, to form a dual-gate transistor.

[0064]FIG. 22 illustrates a substrate 220 (such as a silicon substrate),and an insulator 221, such as many of the insulators discussed above,and a patterned structure 222, such as a silicon structure. In FIG. 23,a mask material 230 is formed along the horizontal surfaces using theprocesses described above. In FIG. 24, the material 222 is laterallypatterned as shown by arrows 240 using the processes described above. Asshown in FIG. 25 the lateral patterning process is continued tocompletely remove the exposed portion of the material 222. Then, asshown in FIG. 26, the insulator 221 and the mask 230 are removed toallow a suspended bridge of the material 222 to remain. A gate insulatorcan be formed on the suspended bridge and a gate conductor can then beformed around the bridge and the remaining well known processing can beperformed to complete the dual gate transistor.

[0065]FIG. 27 is a flow diagram of an embodiment of the invention. Item2700 illustrates the forming of an opening 11 in the substrate 10. Item2701 illustrates protecting a first portion of the vertical walls (mask)of the opening 11. Item 2702 illustrates the lateral patterning of asecond portion 30 of the opening 11, as shown in FIGS. 1-3.

[0066] The inventive lateral patterning process is described above withrespect to a few selected examples. However, the invention is notlimited to the examples discussed. Instead, as would be known by oneordinarily skilled in the art given this disclosure, the invention isapplicable to patterning and forming any structure which is subjected toconventional masking and patterning. The invention is superior toconventional formation techniques because it allows for self-alignedpatterning in the third dimension (i.e., laterally). Also, the size ofthe structures can be easily adjusted by altering of the depth of thesacrificial and/or mask material, as discussed above. The depositions ofthe masking and sacrificial materials can be controlled much moreprecisely with the invention than with conventional lithographictechniques. This is especially true when the dimensions of thestructures decrease.

[0067] While conventional lithographic techniques are optically limitedto certain minimum features sizes, the inventive technique does notutilize optically patterned masks and can, therefore, produce structureswhich are smaller than those that can be produced using lithographicmethods. Self-alignment is key in all high density integrated circuitsand the invention opens the route for three-dimensional integration,since it allows for vertical self-alignment.

[0068] While the invention has been described in terms of preferredembodiments, those skilled in the art will recognize that the inventioncan be practiced with modification within the spirit and scope of theappended claims.

What is claimed is:
 1. A method of forming an integrated circuit chiphaving at least one opening in a substrate, said method comprising:forming an opening having vertical walls in said substrate; protecting afirst portion of said vertical walls of said opening, leaving a secondportion of said vertical walls unprotected; and laterally patterningsaid second portion of said opening to change a property of saidopening.
 2. The method in claim 1 , wherein said laterally patterningcomprises one of an isotropic wet etch, an isotropic dry etch and ananisotropic wet etch.
 3. The method in claim 1 , wherein said protectingcomprises forming a mask over said first portion of said vertical walls.4. The method in claim 1 , wherein said first portion comprises one ofan upper and a lower portion of said opening.
 5. The method in claim 1 ,wherein said first portion and said second portion comprises alternatingportions along a length of said opening.
 6. A method of forming anintegrated circuit chip having at least one opening in a substrate, saidmethod comprising: forming an opening having vertical walls in saidsubstrate; protecting a first portion of said vertical walls of saidopening, leaving a second portion of said vertical walls unprotected;and laterally patterning said second portion of said opening to form astep in said opening.
 7. The method in claim 6 , wherein said laterallypatterning comprises one of an isotropic wet etch, an isotropic dry etchand an anisotropic wet etch.
 8. The method in claim 6 , wherein saidprotecting comprises forming a mask over said first portion of saidvertical walls.
 9. The method in claim 6 , wherein said first portioncomprises a lower portion of said opening.
 10. The method in claim 6 ,wherein said substrate comprises a semiconductor and said method furthercomprises doping selected portions of said step to form two conductiveregions separated by a semiconductive region, wherein in the presence ofan adjacent voltage field, said semiconductive region changes itsconductivity and performs a switching operation in combination with saidconductive regions.
 11. A method of forming an integrated circuit chiphaving at least one transistor, said method comprising: forming anopening having vertical walls in a semiconductor substrate; protecting afirst portion of said vertical walls of said opening, leaving a secondportion of said vertical walls unprotected; laterally patterning saidsecond portion of said opening to form a step in said opening; anddoping selected portions of said step to form two conductive regionsseparated by a semiconductive region, wherein in the presence of anadjacent voltage field, said semiconductive region changes itsconductivity and performs a switching operation in combination with saidconductive regions.
 12. The method in claim 1 1, wherein said laterallypatterning comprises one of an isotropic wet etch, an isotropic dry etchand an anisotropic wet etch.
 13. The method in claim 1 1, wherein saidprotecting comprises forming a mask over said first portion of saidvertical walls.
 14. The method in claim I 1, wherein said first portioncomprises a lower portion of said opening.
 15. A method of forming anintegrated circuit chip having at least one opening in a substrate, saidmethod comprising: forming an opening having vertical walls in saidsubstrate; protecting first portions of said vertical walls of saidopening, leaving second portions of said vertical walls unprotected,wherein said first portions alternate with said second portions; andlaterally patterning said second portions of said opening to change aproperty of said opening.
 16. The method in claim 15 , wherein saidlaterally patterning comprises one of an isotropic wet etch, anisotropic dry etch and an anisotropic wet etch.
 17. The method in claim15 , wherein said protecting comprises forming a mask over said firstportions of said vertical walls.
 18. The method in claim 15 , furthercomprising, after said laterally patterning, lining said opening with aninsulator and filling a remainder of said opening with a conductor toform a deep trench capacitor.
 19. The method in claim 15 , furthercomprising, after said laterally patterning: forming a gate insulator insaid second portions; forming a gate conductor over said gate insulatorin said second portions; doping said first portions to form source anddrain regions; and forming isolation regions over said source and drainregions.
 20. The method in claim 19 , wherein said gate insulator, saidgate conductor, said source and drain regions and said isolation regionscomprise a vertical transistor.
 21. An integrated circuit having atleast one trench capacitor, said trench capacitor comprising: an openinghaving vertical sides, said vertical sides including a plurality oflateral openings; an insulator lining said opening; and a conductorfilling said opening.
 22. The integrated circuit in claim 2 1, whereinsaid lateral openings comprise rectangular openings in cross-section.23. The integrated circuit in claim 21 , wherein said lateral openingscomprise v-shaped openings in cross-section.
 24. The integrated circuitin claim 21 , wherein said lateral openings comprise rounded openings incross-section.
 25. The integrated circuit in claim 21 , wherein saidlateral openings increase a surface area of said trench capacitor. 26.The integrated circuit in claim 21 , wherein said lateral openingsincrease a capacitance of said trench capacitor.